Monday, December 24, 2012

AN5601

Description

The AN5601 is a single chip integrated circuit in which color signal proccesing, video signal proccesing and synchronous signal proccesing circuit for PAL/NTSC color TV are integrated.

Features :

  •  PAL/NTSC Signal Proccesing
  • External RGB Signal input pin provided
  • compatible with teh world the set in combination with SECAM signal proccesing IC
  • Vertical 50/60Hz switching
  • Dual Loop horizontal AFC
  • Sand-Castle pulse output pin provided

Block Diagram

 Download Datasheet AN5601

Friday, December 21, 2012

KA2131


Description

The KA2131 is a monolithic integrated circuit designed for the vertical output stage in color television receivers.

Function 

  • Driver stage
  • Output stage
  • Flyback generators
  • Pulse shapers

Features

  • Low power consumption, direct deflection coil driving capability (Flyback voltage is two times as high as the supply voltage is supplied during flyback period only)
  • High breakdown voltage: 60V

Pinout Diagram

 Download Datasheet KA2131

LA8738

Description


The LA7837, 7838 are vertical deflection output ICs developed for use in high-grade TVs and displays. The interlace and crossover distortion responses, in particular, have been greatly improved, allowing excellent picture quality on large size televisions and high precision interlace mode displays. Also, pulse signals can be used for input signals due to the on-chip sawtooth wave generating circuit and driver circuit. Further, the DC and AC feedback circuit can be formed with these ICs alone, simplifying pattern design of sets and ensuring stable performance. All of the functions in a color TV signal system can be processed by connecting these ICs with SANYO’s single-chip IC LA7670 series (NTSC) and LA7680/85 series (PAL/NTSC) (VIF/SIF, video, chroma, deflection).

The LA7837 has a maximum deflection current of 1.8App, making it appropriate for use in portable to mid-size televisions. The LA7838 has a miximum deflection current of 2.2App, so it can be used for large size sets, and can drive from 33 to 37 inches.

The vertical output ICs LA7837, 7838 are appropriate for use in monitors and displays because the interlace and crossover distortion responses are superior to those of the LA7835, 7836. However, since the vertical retrace time of displays is shorter than that of TV, the upper portion of the vertical picture may stretch. This is because the start waveform of the pin 6 sawtooth wave bends, as shown in Fig.4, due to the diode response of the clamp waveform. If there is not much time difference between T1 ant TR, the upper portion of the vertical picture will tend to stretch. The use of a circuit will cause pin 6 waveform start wave to become linear, so that stretching is suppressed. use the trigger input circuit (pin 2) and one-shot multivibrator (pin 3) built in the LA7837, 7838 ; the pin 6 sawtooth wave is controlled by the LA7855, 7856 vertical output pulse. Therefore, the discharge circuit and clamp circuit are formed by the external Zener diode and transistor TR2.

The LA7837, 7838 can also be used in a vertical frequency multi-sync system. The LA7837, 7838 do not have an on-chip vertical oscillation circuit, so they operate merely by impressing a trigger pulse (e.g. 40 to 80Hz) on pin 2. However, there are two problems with using the LA7837, 7838 as are in a multi-sync system. One is vertical amplitude. When the trigger pulse changes between 40 to 80Hz, the vertical frequency will rise and amplitude size decreases (because pin 6 cycle (T1, T2) in the diagram below becomes shorter).

The vertical output IC LA7837, 7838 are appropriate for use in monitors and displays because the interlace and crossover distortion responses are superior to those of the LA7835, 7836. However, since the vertical retrace time of displays is shorter than that of TV, the upper portion of the vertical picture may stretch. This is because the start waveform of the pin 6 sawtooth wave bends, due to the diode response of the clamp waveform. If there is not much time difference between T1 ant TR, the upper portion of the vertical picture will tend to stretch. The use of a circuit will cause pin 6 waveform start wave to become linear, so that stretching is suppressed.

Features :

  • Low power dissipation due to on-chip pump-up circuit
  • On-chip 50/60Hz vertical size control circuit
  • On-chip sawtooth wave generating circuit
  • On-chip driver circuit
  • Vertical output circuit
  • On-chip thermal protection circuit
  • Excellent interlace response
  • Excellent crossover response

 

Pinout Diagram


Download Datasheet LA8738

STR-W6753

Description


The STR-W6753 is a quasi-resonant regulator specifically designed to satisfy the requirements for increased integration and reliability in switch-mode power supplies. It incorporates a  primary control and drive circuit with an avalanche-rated power MOSFET. The regulator exhibits only low-level high-frequency EMI noise because of soft switching of the MOSFET close to ground (bottom point). A bottom-skip function minimizes an increase of operational frequency during light loads to improve system efficiency over the entire load range. Covering the power range from below 120 watts for a 230 VAC input, or 58 watts for a universal input (85 to 264 VAC), this device can be used in a range of applications, from DVD and VCR players to ac adapters for cellular phones and digital cameras. An auto-standby function, which is internally triggered by sensing on time, reduces power consumption at light load. An externally triggered standby mode reduces the input power further. Multiple protections, including the avalanche-energy-guaranteed MOSFET, provide high reliability of system design. Devices with an increased output power rating are the STR-W6754 and STR-W6756.

Cycle-by-cycle current limiting, undervoltage lockout with hysteresis, and overvoltage protection protect the power supply during the normal overload and fault conditions. Overvoltage protection is latched after a short delay. The latch may be reset by cycling the input supply. Low start-up current and a low-power standby mode selected from the secondary circuit completes a comprehensive suite of features. The STR-W6753 is provided in a fully molded TO-220-style flange mounted, high power, isolated plastic package.

Features :

  • Rugged 650 V Avalanche-Rated MOSFET Simplified Surge Absorption No VDSS Derating Required
  • 1.7 Ω Maximum rDS(on)
  • Two Operational Modes by Automatic Switching: Quasi-Resonant Mode for Normal Operation Burst Mode for Standby Operation or Light Loads
  • Automatic or Manually Triggered Burst Standby Input Power <0.1 W at No Load
  • Auto-Bias Function Stable Burst Operation Without Generating Interference
  • Internal Off-Timer Circuit
  • Built-In Constant-Voltage Drive
  • Multiple Protections:
    Pulse-by-Pulse Over current Protection
    Overload Protection with Auto Recovery
    Latching Over voltage Protection
    Under voltage Lockout with Hysteresis
  • RoHS Compliant

Download Datasheet STR-W6753

ATMEGA128

Description

The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega128 provides the following features: 128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 4Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The ATmega128 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming
the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed.

Features :

  • High-performance, Low-power AVR 8-bit Microcontroller
    • 133 Powerful Instructions - Most Single Clock Cycle Execution 
    • 32 x 8 General Purpose Working Registers + Peripheral Control Resister
    • Up to 16 MIPS Throughput at 16MHz 
    • Fully Static Operation 
    • On-chip 2-cycle Multiplier
  • Non-volatile Program and Data Memories
    • 128k Bytes of In-System Self-Programmable Flash 
    • Optional Boot Code Section with Independent Lock Bits
    • 4K Bytes EEPROM
    • 4K Bytes Internal SRAM
    • Programming Lock for Software Security
    • Up to 64K Bytes Optional External Memory Space 
    • SPI Interface for In-System Programming
  • JTAG Interface
    • Boundary-scan Capabilities According to the JTAG Standard 
    • Extensive On-chip Debug Support 
    • Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAGS Interface
  • Peripheral Features
    • On-chip Analog Comparator 
    • Programmable Watchdog Timer with Seperate On-chip Oscillator
    • Master/Slave SPI Serial Interface
    • Two 8-bit Timer/Counters with Separate Prescalar, Compare
    • Two Expanded 16-bit Timer/Counters with Seperate Prescaler, Compare and Capture mode
    • Real Time Counter with Separate Oscillator
    • Six PWM Channels with Programmable Resolution from 1 to 16 Bits
    • Dual Programmable Serial USARTs
    • 8-channel, 10-bit ADC
    • Byte-oriented Two-wire Serial Interface
    • Four PWM Channels 
    • Dual Programmable Serial USARTs
  • I/O and Packages
    • 53 Programmable I/O Lines 
    • 64-lead TQFP, and 64-pad MLF
  • Operating Voltages
    • 4.5-5.5V for ATmega128
  • Speed Grades
    • 0-16 MHz for ATmega128
  • Special Microcontroller Features
    • Power-on Reset and Programmable Brown-out Detection 
    • Internal Calibrated RC Oscillator
    • External and Internal Interrupt Sources 
    • Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
    • Software selectable Clock Frequence
    • ATmega103 Compatibility Mode Selected by a Fuse
    • Global Pull-up Disable
  •  

Wednesday, December 19, 2012

MAX485

Description


The MAX485 is low-power transceivers for  RS-485 and RS-422 communication. The IC contains one driver and one receiver. The driver slew rates of the MAX485 is not limited, allowing them to transmit up to 2.5Mbps. These transceivers draw between 120μA and 500μA of supply current when unloaded or fully loaded with disabled drivers. All parts operate from a single 5V supply. Drivers are short-circuit current limited and are protected against excessive power dissipation by thermal shutdown circuitry that places the driver outputs into a high-impedance state. The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.

 

Features :

  • Low Quiescent Current: 300μA
  • -7V to +12V Common-Mode Input Voltage Range
  • Three-State Outputs
  • 30ns Propagation Delays, 5ns Skew
  • Operate from a Single 5V Supply
  • Allows up to 32 Transceivers on the Bus
  • Data rate: 2.5 Mbps
  • Current-Limiting and Thermal Shutdown for Driver Overload Protection
  • The transmitter outputs and receiver inputs are protected to ±15kV Air ESD

Application :

  • Low-Power RS-485 Transceivers
  • Low-Power RS-422 Transceivers
  • Level Translators
  • Transceivers for EMI-Sensitive Applications
  • Industrial-Control Local Area Networks

Pinout Diagram

Download Datasheet MAX485

MAX220

Description

The MAX220–MAX249 contain four sections: dual charge-pump DC-DC voltage converters, RS-232 drivers, RS-232 receivers, and receiver and transmitter enable control inputs. The MAX220–MAX249 family of line drivers/receivers is intended for all EIA/TIA-232E and V.28/V.24 communications interfaces, particularly applications where ±12V is not available. These parts are especially useful in battery-powered systems, since their low-power shutdown mode reduces power dissipation to less than 5μW. The MAX225, MAX233, MAX235, and MAX245/MAX246/MAX247 use no external components and are recommended for applications where printed circuit board space is critical.
The MAX220–MAX249 contain four sections: dual charge-pump DC-DC voltage converters, RS-232 drivers, RS-232 receivers, and receiver and transmitter enable control inputs.

Dual Charge-Pump Voltage Converter
The MAX220–MAX249 have two internal charge-pumps that convert +5V to ±10V (unloaded) for RS-232 driver operation. The first converter uses capacitor C1 to double the +5V input to +10V on C3 at the V+ output. The second converter uses capacitor C2 to invert +10V to -10V on C4 at the V- output.
A small amount of power may be drawn from the +10V (V+) and -10V (V-) outputs to power external circuitry, except on the MAX225 and MAX245–MAX247, where these pins are not available. V+ and V- are not regulated, so the output voltage drops with increasing load current. Do not load V+ and V- to a point that violates the minimum ±5V EIA/TIA-232E driver output voltage when sourcing current from V+ and V- to external circuitry. When using the shutdown feature in the MAX222, MAX225, MAX230, MAX235, MAX236, MAX240, MAX241, and MAX245–MAX249, avoid using V+ and V- to power external circuitry. When these parts are shut-down, V- falls to 0V, and V+ falls to +5V. For applications where a +10V external supply is applied to the V+ pin (instead of using the internal charge pump to generate +10V), the C1 capacitor must not be installed and the SHDN pin must be connected to VCC.

RS-232 Drivers
The typical driver output voltage swing is ±8V when loaded with a nominal 5kΩ RS-232 receiver and VCC = +5V. Output swing is guaranteed to meet the EIA/TIA-232E and V.28 specification, which calls for ±5V minimum driver output levels under worst-case conditions. These include a minimum 3kΩ load, VCC = +4.5V, and maximum operating temperature. Unloaded driver output voltage ranges from (V+ -1.3V) to (V- +0.5V). Input thresholds are both TTL and CMOS compatible. The inputs of unused drivers can be left unconnected since 400kΩ input pullup resistors to VCC are built in (except for the MAX220). The pullup resistors force the outputs of unused drivers low because all drivers invert. The internal input pullup resistors typically source 12μA, except in shutdown mode where the pullups are disabled. Driver outputs turn off and enter a high-impedance state—where leakage current is typically microamperes (maximum 25μA)—when in shutdown mode, in three-state mode, or when device power is removed. Outputs can be driven to ±15V. The powersupply current typically drops to 8μA in shutdown mode. The MAX220 does not have pullup resistors to force the outputs of the unused drivers low. Connect unused inputs to GND or VCC. The MAX239 has a receiver three-state control line, and the MAX223, MAX225, MAX235, MAX236, MAX240, and MAX241 have both a receiver three-state control line and a low-power shutdown control. Table 2 shows the effects of the shutdown control and receiver three state control on the receiver outputs.
The receiver TTL/CMOS outputs are in a high-impedance, three-state mode whenever the three-state enable line is high (for the MAX225/MAX235/MAX236/MAX239–MAX241), and are also high-impedance whenever the shutdown control line is high.

RS-232 Receivers
EIA/TIA-232E and V.28 specifications define a voltage level greater than 3V as a logic 0, so all receivers invert. Input thresholds are set at 0.8V and 2.4V, so receivers respond to TTL level inputs as well as EIA/TIA-232E and V.28 levels. The receiver inputs withstand an input over voltage up to ±25V and provide input terminating resistors with nominal 5kΩ values. The receivers implement Type 1 interpretation of the fault conditions of V.28 and EIA/TIA-232E. The receiver input hysteresis is typically 0.5V with a guaranteed minimum of 0.2V. This produces clear output transitions with slow-moving input signals, even with moderate amounts of noise and ringing. The receiver propagation delay is typically 600ns and is independent of input swing direction.

Features :

  • For Low-Voltage, Integrated ESD Applications MAX3222E/MAX3232E/MAX3237E /MAX3241E/ MAX3246E: +3.0V to +5.5V, Low-Power, Up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors (MAX3246E Available in a UCSP™ Package)
  • For Low-Cost Applications, MAX221E: ±15kV ESD-Protected, +5V, 1μA, Single RS-232 Transceiver with AutoShutdown™

Application :

  •  Portable Computers
  • Low-Power Modems
  • Interface Translation
  • Battery-Powered RS-232 Systems
  • Multidrop RS-232 Networks

Pinout Diagram


Download Datasheet MAX220

Tuesday, December 18, 2012

ULN2803

 Description

The ULN2803APG / AFWG Series are high−voltage, high−current darlington drivers comprised of eight NPN darlington pairs. All units feature integral clamp diodes for switching inductive loads. Applications include relay, hammer, lamp and display (LED) drivers. The suffix (G) appended to the part number represents a Lead (Pb)-Free product.

 Features:

  • Output current (single output) 500mA MAX
  • High sustaining voltage output 50V MIN
  • Output clamp diodes
  • Inputs compatible with various types of logic
 

 Pinout Diagram


Download Datasheet ULN2803

ULN2003

Description

The ULN2003 is a monolithic high voltage and high current Darlington transistor arrays. It consists of seven NPN darlington pairs that features high-voltage outputs with common-cathode clamp diode for switching inductive loads. The collector-current rating of a single darlington pair is 500mA. The darlington pairs may be parrlleled for higher current capability. Applications include relay drivers,hammer drivers, lampdrivers,display drivers(LED gas discharge),line drivers, and logic buffers.

The ULN2003 has a 2.7kW series base resistor for each darlington pair for operation directly with TTL or 5V CMOS devices.

Features

  • 500mA rated collector current(Single output)
  • High-voltage outputs: 50V
  • Inputs compatibale with various types of logic
  • Relay driver application

Pinout Diagram

Download Datasheet ULN2003


LM393


Description

The LM393 devices consist of two independent low voltage comparators designed specifically to operate from a single supply over a wide range of voltages. Operation from split power supplies is also possible.

These comparators also have a unique characteristic in that the input common-mode voltage range includes ground even though operated from a single power supply voltage.





Features :

  • Wide single-supply voltage range or dual supplies: +2 V to +36 V or ±1 V to ±18 V
  • Very low supply current (0.45 mA) independent of supply voltage (1 mW/comparator at +5V)
  • Low input bias current: 20 nA typ
  • Low input offset current: ±3 nA typ
  • Low input offset voltage: ±1 mV typ
  • Input common-mode voltage range includes ground
  • Low output saturation voltage: 80 mV typ (Isink = 4 mA)
  • Differential input voltage range equal to the supply voltage
  • TTL, DTL, ECL, MOS, CMOS compatible outputs
  • Available in DIP8, SO-8, TSSOP8, MiniSO-8, and DFN8 2 x 2 mm packages

Pinout Diagram




Download Datasheet LM393

LM319

Description

The LM319 is a dual high speed voltage comparator designed to operate from a single +5V supply up to ±15V dual supplies. Open collector of the output stage makes the LM319 compatible with RTL, DTL and TTL as well as capable of driving lamps and relays at currents up to 25mA. Typical response time of 80ns with ±15V power supplies makes the LM319 ideal for application in fast A/D converts, level shiftier, oscillators, and multivibrators.


 

 

Features :

  • Operates From a Single 5V Supply
  • Typically 80ns Response Time at ±15V
  • Open Collector Outputs : up to +35V
  • High Output Drive Current : 25mA
  • Inputs and Outputs can be Isolated From System Ground
  • Minimum Fan-Out of 2 (Each Side)
  • Two Independent Comparators

Pinout Diagram

Download Datasheet LM319

Monday, December 17, 2012

MAX912CPE

Description

 

The MAX913 (single) and MAX912 (dual) high-speed comparators have a unique design that prevents oscillation when the comparator is in its linear region. No minimum input slew rate is required. Many high-speed comparators oscillate in the linear region, as shown in the Typical Operating Characteristics industry-standard 686 response graph. One way to overcome this oscillation is to sample the output after it has passed through the unstable region. Another practical solution is to add hysteresis. Either solution results in a loss of resolution and bandwidth. Because the MAX912/MAX913 do not need hysteresis, they offer high resolution to all signals—including low frequency signals.
The MAX912/MAX913 provide a TTL-compatible latch function that holds the comparator output state. As long as Latch Enable (LE) is high or floating, the input signal has no effect on the output state. With LE low, the outputs are controlled by the input differential voltage and the latch is transparent.

Input Amplifier
A comparator can be thought of as having two sections: an input amplifier and a logic interface. The MAX912/MAX913’s input amplifier is fully differential, with input offset voltage trimmed to below 2.0mV at +25°C. Input common-mode range extends from 200mV below the negative supply rail to 1.5V below the positive power supply. The total common-mode range is 8.7V when operating from ±5VDC supplies. The MAX912/MAX913’s amplifier has no built-in hysteresis. For highest accuracy, do not add hysteresis.

Resolution
A comparator’s ability to resolve small signal differences-its resolution-is affected by various factors. As with most amplifiers, the most significant factors are the input offset voltage (VOS) and the common-mode and power-supply rejection ratios (CMRR, PSRR). If source impedance is high, input offset current can be significant. If source impedance is unbalanced, the input bias current can introduce another error. For high-speed comparators, an additional factor in resolution is the comparator’s stability in its linear region. Many high-speed comparators are useless in their linear region because they oscillate. This makes the differential input voltage region around 0V unusable, as does a high VOS. Hysteresis does not cure the problem, but acts to keep the input away from its linear range. The MAX912/MAX913 do not oscillate in the linear region, which greatly enhances the comparator’s resolution.

Features :

  • Ultra Fast (10ns)
  • Single +5V or Dual ±5V Supply Operation
  • Input Range Extends Below Negative Supply
  • Low Power: 6mA (+5V) Per Comparator
  • No Minimum Input Signal Slew-Rate Requirement
  • No Power-Supply Current Spiking
  • Stable in the Linear Region
  • Inputs Can Exceed Either Supply
  • Low Offset Voltage: 0.8mV

Application :

  • Zero-Crossing Detectors
  • Ethernet Line Receivers
  • Switching Regulators
  • High-Speed Sampling Circuits
  • High-Speed Triggers
  • Extended Range V/F Converters
  • Fast Pulse Width/Height Discriminators

Applications Information
Power Supplies and Bypassing
The MAX912/MAX913 are tested with ±5V power supplies that provide an input common-mode range (VCM) of 8.7V (-5.2V to +3.5V). Operation from a single +5V supply provides a common-mode input range of 3.7V (-0.2V to +3.5V). Connect V- to GND for single-supply operation. The MAX912/MAX913 will operate from a minimum single-supply voltage of +4.5V. The V+ supply provides power to both the analog input stage and digital output circuits, whereas the V- supply only powers the analog section. Bypass V+ and V- to ground with 0.1μF to 1.0μF ceramic capacitors in parallel with 10μF or greater tantalum capacitors. Connect the ceramic capacitors very close to the MAX912/MAX913’s supply pins, keeping leads short to minimize lead inductance. For particularly noisy applications, use ferrite beads on the power-supply lines.

Input Slew Rate
The MAX912/MAX913 design eliminates the input slew rate requirement imposed on many standard comparators. As long as LE is high after the maximum propagation delay and the input is greater than the comparator total DC error, the output will be valid without oscillations.

Maximum Clock (LE) and Signal Rate
The maximum clock and signal rate is 70MHz, based on the comparator’s rise and fall time with a 5mV overdrive at +25°C (Figure 1). With a 20mV overdrive, the maximum propagation delay is 12ns and the clock and signal rate is 85MHz.

Pinout Diagram


Download Datasheet MAX912CPE

LM311

Description

 

The LM311 series is a monolithic, low input current voltage comparator. The device is also designed to operate from dual or single supply voltage.



Features :

  • Low input bias current : 250nA (Max)
  • Low input offset current : 50nA (Max)
  • Differential Input Voltage : ±30V
  • Power supply voltage : single 5.0V supply to ±15V
  • Offset voltage null capability
  • Strobe capability

Pinout Diagram

Download Datasheet LM311


AP331A

Description

The AP331A is a precision voltage comparators with an offset voltage specification as low as 8.0 mV max for comparator which were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. The comparator also have a unique characteristic in that the input common-mode voltage range includes ground, even though operated from a single power supply voltage.

Application areas include limit comparators, simple analog to digital converters; pulse, square wave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The AP331A is designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, the AP331A will directly interface with MOS logic where their low power drain is a distinct advantage over standard comparators.


Features :

  • Wide supply
    Voltage range: 2.0V to 36V
    Single or dual supplies: ±1.0V to ±18V
  • Very low supply current drain (0.4mA) – independent of supply voltage
  • Low input biasing current: 150nA
  • Low input offset current: ±70nA
  • Low input offset voltage: ±4mV
  • Input common-mode voltage range includes ground
  • Differential input voltage range equal to the power supply voltage
  • Low output saturation voltage: 250mV at 4mA
  • Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems
  • SOT25 and SOT25R: Available in “Green” Molding Compound (No Br, Sb)
  • Lead Free Finish/ RoHS Compliant

Application :

  • High precision comparators
  • Reduced VOS drift over temperature
  • Eliminates need for dual supplies
  • Allows sensing near ground
  • Compatible with all forms of logic
  • Power drain suitable for battery operation
Application Information
The AP331A is high gain, wide bandwidth devices, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator change states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to < 10kΩ reduces the feedback signal levels and finally, adding even a small amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All input pins of any unused comparators should be tied to the negative supply.
The bias network of the AP331A establishes a drain current independent of the magnitude of the power supply voltage over the range of from 2.0 VDC to 30 VDC. It is usually unnecessary to use a bypass capacitor across the power supply line. The differential input voltage may be larger than V+ without damaging the device (Note 10). Protection should be provided to prevent the input voltages from going negative more than -0.3 VDC (at 25°C). An input clamp diode can be used as shown in the applications section.
The output of the AP331A is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR’ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage applied to the V+ terminal of the AP331A package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current the output device can sink is limited by the drive available (which is independent of V+) and the β of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The  output saturation voltage is limited by the approximately 60Ω rSAT of the output transistor. The low offset voltage of the output transistor (1.0 mV) allows the output to clamp essentially to ground level for small load currents.

Pinout Diagram




Download Datasheet AP331A

MAX941CPA

Description

The MAX941/MAX942/MAX944 single-supply comparators feature internal hysteresis, high speed, and low power. Their outputs are guaranteed to pull within 0.4V of either supply rail without external pull-up or pull-down circuitry. Rail-to-rail input voltage range and low voltage single-supply operation make these devices ideal for portable equipment. The MAX941/MAX942/MAX944 interface directly to CMOS and TTL logic.

Timing
Most high-speed comparators oscillate in the linear region because of noise or undesired parasitic feedback.
This tends to occur when the voltage on one input is at or equal to the voltage on the other input. To counter the parasitic effects and noise, the MAX941/MAX942/MAX944 have internal hysteresis. The hysteresis in a comparator creates two trip points: one for the rising input voltage and one for the falling input voltage.
The difference between the trip points is the hysteresis. When the comparator’s input voltages are equal, the hysteresis effectively causes one comparator input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. Standard comparators require hysteresis to be added with external resistors. The MAX941/MAX942/MAX944’s fixed internal hysteresis  eliminates these resistors and the equations needed to determine appropriate values.
The MAX941 includes an internal latch that allows storage of comparison results. The LATCH pin has a high input impedance. If  LATCH is high, the latch is transparent (i.e., the comparator operates as though the latch is not present). The comparator's output state is stored when LATCH is pulled low. All timing  constraints must be met when using the latch function.

Shutdown Mode
The MAX941 shuts down when SHDN is low. When shutdown, the supply current drops to less than 30μA, and the three-state output becomes high impedance. The SHDN pin has a high input impedance. Connect SHDN to V+ for normal operation. Exit shutdown with LATCH high; otherwise, the output will be indeterminate.

Input Stage Circuitry
The MAX941/MAX942/MAX944 include internal protection circuitry that prevents damage to the precision
input stage from large differential input voltages. This protection circuitry consists of four back-to-back diodes between IN+ and IN- as well as two 2.5k½ resistors. The diodes limit the differential voltage applied to the internal circuitry of the comparators to be no more than 4VF, where VF is the forward voltage drop of the diode (about 0.7V at +25°C). For a large differential input voltage (exceeding 4VF), this protection circuitry increases the input bias current at IN+ (source) and IN- (sink).

Input Current =(IN+ - IN-) - 4VF
                              2 x 2.5k½

Input current with large differential input voltages should not be confused with input bias current (IB). As long as the differential input voltage is less than 4VF, this input current is equal to IB. The protection circuitry also allows for the input common-mode range of the MAX941/MAX942/MAX944 to extend beyond both power-supply rails. The output is in the correct logic state if one or both inputs are within the common-mode range.

Output Stage Circuitry
The MAX941/MAX942/MAX944 contain a current-driven output stage as shown in Figure 4. During an output transition, ISOURCE or ISINK is pushed or pulled to the output pin. The output source or sink current is high during the transition, creating a rapid slew rate. Once the output voltage reaches VOH or VOL, the source or sink current decreases to a small value, capable of maintaining the VOH or VOL static condition. This significant decrease in current conserves power after an output transition has occurred.
One consequence of a current-driven output stage is a linear dependence between the slew rate and the load capacitance. A heavy capacitive load will slow down a voltage output transition. This can be useful in noise sensitive applications where fast edges may cause interference.

Features :

  •  In μMAX Package: Smallest 8-Pin SO
  • Optimized for 3V and 5V Applications (operation down to 2.7V)
  • Fast, 80ns Propagation Delay (5mV overdrive)
  • Rail-to-Rail Input Voltage Range
  • Low Power:
    1mW Power Dissipation per Comparator (3V)
    350μA Supply Current
  • Low, 1mV Offset Voltage
  • Internal Hysteresis for Clean Switching
  • Outputs Swing 200mV of Power Rails
  • CMOS/TTL-Compatible Output
  • Output Latch
 

Applications :

  • 3V/5V Systems
  • Battery-Powered Systems
  • Threshold Detectors/Discriminators
  • Line Receivers
  • Zero-Crossing Detectors
  • Sampling Circuits

Pinout Diagram

Download Datasheet MAX941CPA


ATMEGA32

Description

The Atmel®AVR®AVR core combines a rich instruction set with 32general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega32 provides the following features: 32Kbytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 1024bytes EEPROM, 2Kbyte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundaryscan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillatorand the Asynchronous Timer continue to run.

Features

  • High-performance, Low-power Atmel®AVR® 8-bit Microcontroller
  • Advanced RISC Architecture
    – 131 Powerful Instructions – Most Single-clock Cycle Execution
    – 32 × 8 General Purpose Working Registers
    – Fully Static Operation
    – Up to 16 MIPS Throughput at 16MHz
    – On-chip 2-cycle Multiplier
  • High Endurance Non-volatile Memory segments
    – 32Kbytes of In-System Self-programmable Flash program memory
    – 1024Bytes EEPROM
    – 2Kbytes Internal SRAM
    – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
    – Data retention: 20 years at 85°C/100 years at 25°C(1)
    – Optional Boot Code Section with Independent Lock Bits
       In-System Programming by On-chip Boot Program
       True Read-While-Write Operation
    – Programming Lock for Software Security
  • JTAG (IEEE std. 1149.1 Compliant) Interface
    – Boundary-scan Capabilities According to the JTAG Standard
    – Extensive On-chip Debug Support
    – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
  • Peripheral Features
    – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
    – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
    – Real Time Counter with Separate Oscillator
    – Four PWM Channels
    – 8-channel, 10-bit ADC
       8 Single-ended Channels
       7 Differential Channels in TQFP Package Only
       2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
    – Byte-oriented Two-wire Serial Interface
    – Programmable Serial USART
    – Master/Slave SPI Serial Interface
    – Programmable Watchdog Timer with Separate On-chip Oscillator
    – On-chip Analog Comparator
  • Special Microcontroller Features
    – Power-on Reset and Programmable Brown-out Detection
    – Internal Calibrated RC Oscillator
    – External and Internal Interrupt Sources
    – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
       and Extended Standby
  • I/O and Packages
    – 32 Programmable I/O Lines
    – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
  • Operating Voltages
    – 2.7V - 5.5V for ATmega32L
    – 4.5V - 5.5V for ATmega32
  • Speed Grades
    – 0 - 8MHz for ATmega32L
    – 0 - 16MHz for ATmega32
  • Power Consumption at 1MHz, 3V, 25°C
    – Active: 1.1mA
    – Idle Mode: 0.35mA
    – Power-down Mode: < 1μA

Pinout Diagram

Download Datasheet ATMEGA32

ATMEGA16


 Description

The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The ATmega16 provides the following features: 16 Kbytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1 Kbyte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundaryscan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

Features:

  • High-performance, Low-power Atmel® AVR® 8-bit Microcontroller
  • Advanced RISC Architecture
    – 131 Powerful Instructions – Most Single-clock Cycle Execution
    – 32 x 8 General Purpose Working Registers
    – Fully Static Operation
    – Up to 16 MIPS Throughput at 16 MHz
    – On-chip 2-cycle Multiplier
  • High Endurance Non-volatile Memory segments
    – 16 Kbytes of In-System Self-programmable Flash program memory
    – 512 Bytes EEPROM
    – 1 Kbyte Internal SRAM
    – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
    – Data retention: 20 years at 85°C/100 years at 25°C(1)
    – Optional Boot Code Section with Independent Lock Bits
       In-System Programming by On-chip Boot Program
       True Read-While-Write Operation
    – Programming Lock for Software Security
  • JTAG (IEEE std. 1149.1 Compliant) Interface
    – Boundary-scan Capabilities According to the JTAG Standard
    – Extensive On-chip Debug Support
    – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface]
  • Peripheral Features
    – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
    – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
    – Real Time Counter with Separate Oscillator
    – Four PWM Channels
    – 8-channel, 10-bit ADC
       8 Single-ended Channels
       7 Differential Channels in TQFP Package Only
       2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
    – Byte-oriented Two-wire Serial Interface
    – Programmable Serial USART
    – Master/Slave SPI Serial Interface
    – Programmable Watchdog Timer with Separate On-chip Oscillator
    – On-chip Analog Comparator
  • Special Microcontroller Features
    – Power-on Reset and Programmable Brown-out Detection
    – Internal Calibrated RC Oscillator
    – External and Internal Interrupt Sources
    – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
       and Extended Standby
  • I/O and Packages
    – 32 Programmable I/O Lines
    – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
  • Operating Voltages
    – 2.7V - 5.5V for ATmega16L
    – 4.5V - 5.5V for ATmega16
  • Speed Grades
    – 0 - 8 MHz for ATmega16L
    – 0 - 16 MHz for ATmega16
  • Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L
    – Active: 1.1 mA
    – Idle Mode: 0.35 mA
    – Power-down Mode: < 1 μA

Pinout Diagram

ATMEGA168


 

 

 

 

 Description

 

The Atmel ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The Atmel ATmega48/88/168 provides the following features: 4K/8K/16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

Features :

  • High performance, low power Atmel® AVR® 8-bit microcontroller
  • Advanced RISC architecture
    – 131 powerful instructions – most single clock cycle execution
    – 32 × 8 general purpose working registers
    – Fully static operation
    – Up to 20 MIPS throughput at 20MHz
    – On-chip 2-cycle multiplier
  • High endurance non-volatile memory segments
    – 4/8/16 Kbytes of in-system self-programmable flash program memory
    – 256/512/512 bytes EEPROM
    – 512/1K/1Kbytes internal SRAM
    – Write/erase cyles: 10,000 flash/100,000 EEPROM
    – Data retention: 20 years at 85°C/100 years at 25°C()
    – Optional boot code section with independent lock bits
          In-system programming by on-chip boot program
          True read-while-write operation
    – Programming lock for software security
  • QTouch® library support
    – Capacitive touch buttons, sliders and wheels
    – QTouch and QMatrix acquisition
    – Up to 64 sense channels
  • Peripheral features
    – Two 8-bit timer/counters with separate prescaler and compare mode
    – One 16-bit timer/counter with separate prescaler, compare mode, and capture mode
    – Real time counter with separate oscillator
    – Six PWM channels
    – 8-channel 10-bit ADC in TQFP and QFN/MLF package
    – 6-channel 10-bit ADC in PDIP Package
    – Programmable serial USART
    – Master/slave SPI serial interface
    – Byte-oriented 2-wire serial interface (Philips I2C compatible)
    – Programmable watchdog timer with separate on-chip oscillator
    – On-chip analog comparator
    – Interrupt and wake-up on pin change
  • Special microcontroller features
    – DebugWIRE on-chip debug system
    – Power-on reset and programmable brown-out detection
    – Internal calibrated oscillator
    – External and internal interrupt sources
    – Five sleep modes: Idle, ADC noise reduction, power-save, power-down, and standby
  • I/O and packages
    – 23 programmable I/O lines
    – 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
  • Operating voltage:
    – 1.8V - 5.5V for Atmel ATmega48V/88V/168V
    – 2.7V - 5.5V for Atmel ATmega48/88/168
  • Temperature range:
    – -40°C to 85°C
  • Speed grade:
    – ATmega48V/88V/168V: 0 - 4MHz @ 1.8V - 5.5V, 0 - 10MHz @ 2.7V - 5.5V
    – ATmega48/88/168: 0 - 10MHz @ 2.7V - 5.5V, 0 - 20MHz @ 4.5V - 5.5V
  • Low power consumption
    – Active mode:
       250μA at 1MHz, 1.8V
       15μA at 32kHz, 1.8V (including oscillator)
    – Power-down mode:
       0.1μA at 1.8V 
     

Pinout Diagram


 Download Datasheet ATMEGA168

ATMEGA8

 Description

 

The Atmel®AVR® ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

The Atmel®AVR® AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

Features :

  •  High-performance, Low-power Atmel®AVR® 8-bit Microcontroller
  • Advanced RISC Architecture
    – 130 Powerful Instructions – Most Single-clock Cycle Execution
    – 32 x 8 General Purpose Working Registers
    – Fully Static Operation
    – Up to 16MIPS Throughput at 16MHz
    – On-chip 2-cycle Multiplier
  • High Endurance Non-volatile Memory segments
    – 8KBytes of In-System Self-programmable Flash program memory
    – 512Bytes EEPROM
    – 1KByte Internal SRAM
    – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
    – Data retention: 20 years at 85°C/100 years at 25°C(1)
    – Optional Boot Code Section with Independent Lock Bits
       • In-System Programming by On-chip Boot Program
       • True Read-While-Write Operation
    – Programming Lock for Software Security
  • Peripheral Features
    – Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
    – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
    Mode
    – Real Time Counter with Separate Oscillator
    – Three PWM Channels
    – 8-channel ADC in TQFP and QFN/MLF package
        • Eight Channels 10-bit Accuracy
    – 6-channel ADC in PDIP package
        • Six Channels 10-bit Accuracy
    – Byte-oriented Two-wire Serial Interface
    – Programmable Serial USART
    – Master/Slave SPI Serial Interface
    – Programmable Watchdog Timer with Separate On-chip Oscillator
    – On-chip Analog Comparator
  • Special Microcontroller Features
    – Power-on Reset and Programmable Brown-out Detection
    – Internal Calibrated RC Oscillator
    – External and Internal Interrupt Sources
    – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
  • I/O and Packages
    – 23 Programmable I/O Lines
    – 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
  • Operating Voltages
    – 2.7 - 5.5V
    – 0 - 16MHz
  • Power Consumption at 4MHz, 3V, 25°C
    – Active: 3.6mA
    – Idle Mode: 1.0mA
    – Power-down Mode: 0.5μA

Pinout Diagram

Download Datasheet ATMEGA8

ATMEGA8535L

Description


The high-performance, low-power Atmel 8-bit AVR RISC-based microcontroller combines 8KB of programmable flash memory, 544B SRAM, 512B EEPROM, and an 8-channel 10-bit A/D converter. The device supports throughput of 16 MIPS at 16MHz and operates between 4.5-5.5 volts. By executing instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz, balancing power consumption and processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8535 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 32 general purpose I/O lines, 32general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain in TQFP package, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run.

Features :

  • High-performance, Low-power AVR® 8-bit Microcontroller
  • Advanced RISC Architecture
    – 130 Powerful Instructions – Most Single Clock Cycle Execution
    – 32 x 8 General Purpose Working Registers
    – Fully Static Operation
    – Up to 16 MIPS Throughput at 16 MHz
    – On-chip 2-cycle Multiplier
  • Nonvolatile Program and Data Memories
    – 8K Bytes of In-System Self-Programmable Flash
       Endurance: 10,000 Write/Erase Cycles
    – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation
    – 512 Bytes EEPROM
       Endurance: 100,000 Write/Erase Cycles
    – 512 Bytes Internal SRAM
    – Programming Lock for Software Security
  • Peripheral Features
    – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
    – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
    – Real Time Counter with Separate Oscillator
    – Four PWM Channels
    – 8-channel, 10-bit ADC
    8 Single-ended Channels
    7 Differential Channels for TQFP Package Only
    2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP
    Package Only
    – Byte-oriented Two-wire Serial Interface
    – Programmable Serial USART
    – Master/Slave SPI Serial Interface
    – Programmable Watchdog Timer with Separate On-chip Oscillator
    – On-chip Analog Comparator
  • Special Microcontroller Features
    – Power-on Reset and Programmable Brown-out Detection
    – Internal Calibrated RC Oscillator
    – External and Internal Interrupt Sources
    – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
       and Extended Standby
  • I/O and Packages
    – 32 Programmable I/O Lines
    – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
  • Operating Voltages
    – 2.7 - 5.5V for ATmega8535L
    – 4.5 - 5.5V for ATmega8535
  • Speed Grades
    – 0 - 8 MHz for ATmega8535L
    – 0 - 16 MHz for ATmega8535

Pinout Diagram

Download Datasheet ATMEGA8535

ATMEGA8515


 

Description


The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The ATmega8515 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, an External memory interface, 35 general purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with compare modes, Internal and External interrupts, a Serial Programmable USART, a programmable Watchdog Timer with internal Oscillator, a SPI serial port, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt system to continue functioning. The Power-down mode saves the Register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP Flash allows the Program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

Features :

  • High-performance, Low-power AVR® 8-bit Microcontroller
  • RISC Architecture
    – 130 Powerful Instructions – Most Single Clock Cycle Execution
    – 32 x 8 General Purpose Working Registers
    – Fully Static Operation
    – Up to 16 MIPS Throughput at 16 MHz
    – On-chip 2-cycle Multiplier
  • Nonvolatile Program and Data Memories
    – 8K Bytes of In-System Self-programmable Flash
       Endurance: 10,000 Write/Erase Cycles
    – Optional Boot Code Section with Independent Lock bits
       In-System Programming by On-chip Boot Program
       True Read-While-Write Operation
    – 512 Bytes EEPROM
       Endurance: 100,000 Write/Erase Cycles
    – 512 Bytes Internal SRAM
    – Up to 64K Bytes Optional External Memory Space
    – Programming Lock for Software Security
  • Peripheral Features
    – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
    – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
    – Three PWM Channels
    – Programmable Serial USART
    – Master/Slave SPI Serial Interface
    – Programmable Watchdog Timer with Separate On-chip Oscillator
    – On-chip Analog Comparator
  • Special Microcontroller Features
    – Power-on Reset and Programmable Brown-out Detection
    – Internal Calibrated RC Oscillator
    – External and Internal Interrupt Sources
    – Three Sleep Modes: Idle, Power-down and Standby
  • I/O and Packages
    – 35 Programmable I/O Lines
    – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
  • Operating Voltages
    – 2.7 - 5.5V for ATmega8515L
    – 4.5 - 5.5V for ATmega8515
  • Speed Grades
    – 0 - 8 MHz for ATmega8515L
    – 0 - 16 MHz for ATmega8515

Pinout Diagram


Download Datasheet ATMEGA8515