CD4066B

Description

The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B is recommended.

Features:

• 15-V Digital or ±7.5-V Peak-to-Peak Switching
• 125-Ω Typical On-State Resistance for 15-V Operation
• Switch On-State Resistance Matched to Within 5 Ω Over 15-V Signal-Input Range
• On-State Resistance Flat Over Full Peak-to-Peak Signal Range
• High On/Off Output-Voltage Ratio: 80 dB Typical at fis = 10 kHz, RL = 1 kΩ
• High Degree of Linearity: <0.5% Distortion Typical at fis = 1 kHz, Vis = 5 V p-p, VDD − VSS ≥ 10 V, RL = 10 kΩ
• Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10 pA Typical at VDD − VSS = 10 V, TA = 25°C
• Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit): 1012 Ω Typical
• Low Crosstalk Between Switches: −50 dB Typical at fis = 8 MHz, RL = 1 kΩ
• Matched Control-Input to Signal-Output Capacitance: Reduces Output Signal Transients
• Frequency Response, Switch On = 40 MHz Typical
• 100% Tested for Quiescent Current at 20 V
• 5-V, 10-V, and 15-V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13-B, Standard Specifications for Description of “B” Series CMOS Devices

Apllications:

• Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch
• Digital Signal Switching/Multiplexing
• Transmission-Gate Logic Implementation
• Analog-to-Digital and Digital-to-Analog Conversion
• Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain

Pinout CD4066

 Download Datasheet CD4066B

TLC072CP

 Description

The JFET-input operational amplifiers in the TL07_ series are designed as low-noise versions of the TL08_ series amplifiers with low input bias and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07_ series ideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from –40°C to 85°C. The M-suffix devices are characterized for operation over the full military temperature range of –55°C to 125°C.

Features:

• Low Power Consumption
• Wide Common-Mode and Differential Voltage Ranges
• Low Input Bias and Offset Currents
• Output Short-Circuit Protection
• Low Total Harmonic Distortion 0.003% Typ
• Low Noise Vn = 18 nV//Hz Typ at f = 1 kHz
• High Input Impedance . . . JFET Input Stage
• Internal Frequency Compensation
• Latch-Up-Free Operation
• High Slew Rate . . . 13 V/ms Typ
• Common-Mode Input Voltage Range Includes VCC+

Pin Connection

Download Datasheet TL072CP

NE555

Desription


TheNE555monolithic timing circuit isa highlystable controller capableofproducingaccuratetime delays or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200mA. The NE555 is available in plastic and ceramic mini dip package and in a 8-lead micro package and in metal can package version.

Features

• Low turn OFF time
• Maximum operating frequency greater han 500kHz
• Timing from micro seconds to hours
• Operates in both astable and monostable modes
• High output current can source or sink 200mA
• TTL Compatible
• Temperature stability of 0.0005% PeroC

Pin Connection

 Download Datasheet NE555

ATMEGA64

Description

The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general  purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega64 provides the following features: 64 Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal  Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run.

Pinout ATMEGA64

Download Datasheet ATMEGA64

AT89C51

Description

 The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.


Features

• Compatible with MCS-51™ Products
• 4K Bytes of In-System Reprogrammable Flash Memory
• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes

Pinout Diagram

Download Datasheet AT89C51