Description
These are the first monolithic JFET input
operational amplifiers to incorporate well matched, high voltage JFETs
on the same chip with standard bipolar transistors (BI-FET™ Technology).
These amplifiers feature low input bias and offset currents / low offset
voltage and offset voltage drift, coupled with offset adjust which does
not degrade drift or common-mode rejection. The devices are also
designed for high slew rate, wide bandwidth, extremely fast settling
time, low voltage and current noise and a low 1/f noise corner.
Features :
- High inpit impedance J_FET input stage
- High speed J-FET OP-Amps : Uup to 20MHz 50V/ms
- Offset Voltage adjust doesn't Degraded drift or common-mode rejection as in most monolithic
- Internal compensation and large differential input voltage capability (up to VCC+)
Typical Applications :
- Precision High Speed Integratos
- Fast D/A and A/D Converters
- High Impedance Buffers
- Wide band, Low Noise, Low Drift amplifier
- Logarithmic amplifier
- Photocell amplifier
Application Hints
The LF155, LF156, LF157 series are op amps with JFET input transistors. These JFETs have large reverse
breakdown voltages from gate to source or drain eliminating the need of clamps across the inputs.Therefore
large differential input voltages can easily be accommodated without a large increase of input currents.
The maximum differential input voltage is independent of the supply voltage. However, neither of the negative input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which
can result in a destroyed unit.
Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state.
These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the
common-mode voltage can exceed the positive supply by approximately 100mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter.
Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not in advertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit.
Because these amplifiers are JFET rather than MOSFET input op amps they do not require special handling. All of the bias currents in these amplifiers a reset by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltages.
As with most amplifiers, care should be taken with lead dress, components placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body
close to the input to minimize ”pickup” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and
capacitance from the input of the device(usually the inverting input) to ac ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six time the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of that added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.
Pin Out Diagram :
Pin 2 : Input
Pin 3 : Input
Pin 4: V (-)
Pin 5 : Balance
Pin 6 : Output
Pin 7 : V (+)
Pin 8 : NC
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