DescriptionThe AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
- Utilizes the AVR® RISC Architecture
- AVR – High-performance and Low-power RISC Architecture
– 89 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 12 MIPS Throughput at 12 MHz
- Data and Non-volatile Program Memory
– 1K Byte of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
- Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
- Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Selectable On-chip RC Oscillator for Zero External Components
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
- Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.0 mA
– Idle Mode: 0.4 mA
– Power-down Mode: <1 μA
- I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP, SOIC and SSOP
- Operating Voltages
– 2.7 - 6.0V (AT90S1200-4)
– 4.0 - 6.0V (AT90S1200-12)
- Speed Grades
– 0 - 4 MHz, (AT90S1200-4)
– 0 - 12 MHz, (AT90S1200-12)
Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. The AVR uses a Harvard architecture concept – with separate memories and buses for program and data memories. The program memory is accessed with a 2-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate
interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.