Friday, December 21, 2012



The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega128 provides the following features: 128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 4Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The ATmega128 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming
the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed.

Features :

  • High-performance, Low-power AVR 8-bit Microcontroller
    • 133 Powerful Instructions - Most Single Clock Cycle Execution 
    • 32 x 8 General Purpose Working Registers + Peripheral Control Resister
    • Up to 16 MIPS Throughput at 16MHz 
    • Fully Static Operation 
    • On-chip 2-cycle Multiplier
  • Non-volatile Program and Data Memories
    • 128k Bytes of In-System Self-Programmable Flash 
    • Optional Boot Code Section with Independent Lock Bits
    • 4K Bytes EEPROM
    • 4K Bytes Internal SRAM
    • Programming Lock for Software Security
    • Up to 64K Bytes Optional External Memory Space 
    • SPI Interface for In-System Programming
  • JTAG Interface
    • Boundary-scan Capabilities According to the JTAG Standard 
    • Extensive On-chip Debug Support 
    • Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAGS Interface
  • Peripheral Features
    • On-chip Analog Comparator 
    • Programmable Watchdog Timer with Seperate On-chip Oscillator
    • Master/Slave SPI Serial Interface
    • Two 8-bit Timer/Counters with Separate Prescalar, Compare
    • Two Expanded 16-bit Timer/Counters with Seperate Prescaler, Compare and Capture mode
    • Real Time Counter with Separate Oscillator
    • Six PWM Channels with Programmable Resolution from 1 to 16 Bits
    • Dual Programmable Serial USARTs
    • 8-channel, 10-bit ADC
    • Byte-oriented Two-wire Serial Interface
    • Four PWM Channels 
    • Dual Programmable Serial USARTs
  • I/O and Packages
    • 53 Programmable I/O Lines 
    • 64-lead TQFP, and 64-pad MLF
  • Operating Voltages
    • 4.5-5.5V for ATmega128
  • Speed Grades
    • 0-16 MHz for ATmega128
  • Special Microcontroller Features
    • Power-on Reset and Programmable Brown-out Detection 
    • Internal Calibrated RC Oscillator
    • External and Internal Interrupt Sources 
    • Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
    • Software selectable Clock Frequence
    • ATmega103 Compatibility Mode Selected by a Fuse
    • Global Pull-up Disable

No comments:

Post a Comment